**ENEE**** ****411**** ****Summer**** ****2022**

**Homework**** ****2**

1. Problems 6.24 (Baker 4^{th} ed) __(60____ ____points)__

Estimate, in terms of *V*_{DD} and *I _{OFFn,p}* (the off current of either the NMOS or PMOS devices), the power dissipated in each of the following circuits. Which device dissipates power in each circuit?

2. Problems 9.5 (Baker 4^{th} ed) __(60____ ____points)__

Calculate I_{D, }V_{DS, } and estimate the small-signal resistance looking into the drain of the MOSFET in the following circuit.

3. Problem 9.33 (Baker 4^{th} ed) __(40____ ____points)__

Using the process data for short-channel (50 nm) length MOSFET, and the square-law equations, determine the DC voltage,*V _{x }*in each of the following circuits.

4. Problem 9.38 & 9.39 (Baker 4^{th} ed) __(50 points)__

Estimate the AC current, *ii _{T }*that flows in the test voltage

*v*_{T/}_{Rcℎ}* V*T/Rch for triode operation (see Eq. [9.16] in Baker). The resistance seen by *v*_{T} is then the parallel combination of the resistors.

5. Problem 20.1 (Baker 4^{th} ed) __(50 points)__

Using the CMOS long-channel process (1*μ*m), determine the current flowing in the circuit seen below.

6. Using the CMOS long-channel process (1*μ*m), calculate the currents and voltages in the circuit seen below. What is the maximum value allowed for *R*_{2} so that M2 remains operating in the saturation region?

7. Problem 21.3 (Baker 4^{th} ed) __(50____ ____points)__

Estimate the frequency response of the circuit seen below if the amplifier drives a 100 *f *F load capacitance.

8. Using the CMOS long-channel process (*μ*m), estimate the AC and DC drain currents in the circuit seen in the figure below. What are *v*_{gs1}* _{ }*and

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